Informatics Publishing Limited

P. Arivazhagan ¹, P. Kanmani ¹, J. Manikandan ²

Affiliations
1 Department of Computer Science and Engineering, K. S. Rangasamy College of Technology, Tamilnadu, IN
2 Department of Information Technology, K. S. Rangasamy College of Technology, Tamilnadu, IN

Abstract

The objective of cooperative caching is to improve data availability, improve access efficiency and reduce query delay in mobile Ad-Hoc networks. Many types of cache replacement algorithms like LRU, LFU, LFRU, LRU-MIN and LFU-MIN are used to improve data accessibility and reduce query delay in cluster based cooperative caching in Mobile Ad-Hoc networks. But they have some limitations such as accessing remote information station via multi hop communication leads to longer query latency and causes high energy consumption, many clients frequently access the database server they cause a high load on the server and reduce the server response time .Multi hop communication causes the network capacity degrades when network partition occurs. The paper gives an overview of Cooperative Cache Management Techniques and caching policies and propose a new algorithm can be regarded as a LRFU-MIN (least recently frequently used information with minimal number of page replacements). It discover a data source which induces less communication cost of moving cache blocks into the most recently frequently used position and minimizes caching duplications between neighbor nodes. In this paper we utilize a cross-layer design approach to improve the performance of combined cooperative caching and prefetching schemes. The paper examines the performance using NS-2 simulation environments. The proposed LRFU-MIN enhances the performance of cross-layer cluster based cooperative caching in mobile Ad-Hoc networks when compared with LRU and LFU-MIN.

Keywords

Adhoc Networks, Cooperative Caching, Clustering, Data Caching, Information Search.

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J. Manikandan ¹, M. Manikandan ²

Affiliations
1 Department of ECE, Sri Sai Ram Engineering College, Chennai - 600044, Tamil Nadu, IN
2 Department of Electronics,MIT Campus, Anna University, Chennai - 600044, Tamil Nadu, IN

Abstract

Background: Fast Fourier Transform (FFT) operation is one of the most important fundamental operations in the digital signal processing systems. In this paper, a new pipelined Radix-8 based Fast Fourier Transformation (FFT) architecture is designed for performing frequency transformation techniques. The objective of this paper is to improve the speed and to reduce the area, delay and power. Methods: Radix-8 FFT, which is used to improve the speed of functioning by reducing the computational path. In the proposed new architecture named as “Radix-8 combined SDF-SDC FFT”. In this architecture, the numbers of stages are reduced to 75%. The first two stages are designed using Single path delay feedback and the last two stages are designed using single-path-delay Commutator. The combined SDF-SDC FFT is to increasing the processing speed of architecture. In the proposed “pipelined Radix-8 combined SDF-SDC FFT’’ is designed in this article. Findings: In the existing Radix-8 SDF FFT, the number of stages is increased. In order to reduce the number of stages, Radix-8 combined SDF-SDC FFT has been proposed. The performance evaluation of Radix-8 combined SDF-SDC FFT architecture is determined through Very Large Scale Integration (VLSI) system design environment. In the VLSI system design, less area utilization, low power consumption and high speed are the main parameters. Hence, the main goal of proposed architecture is to reduce hardware complexity, power consumption and increasing both speed and throughput of the system. Applications: Mobile Ad-hoc Network (MANET), Orthogonal Frequency Division Multiplexing (OFDM) System, Telecommunication networking system are considered as the important applications of proposed radix-8 combined SDF-SDC FFT.

Keywords

Fast Fourier Transform (FFT), Single-path Delay Commutator (SDC) FFT, Single-path Delay Feedback (SDF) FFT, Very Large Scale Integration (VLSI).

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